Please refer to FIG. 1 which describes the flow of recording data to a Digital Versatile Disc (DVD). General, a DVD 60 can record various types of digital information 10, such as video, audio, data and other analog data that has been converted to corresponding digital data via some digital to analogue (A/D) conversion. As illustrated by FIG. 1, digital data 10 need to go through data compression 20, data security 30, error correction 40 and modulation/demodulation 50 in order to have data written in or data retrieve from the disc.
In greater details, when recording digital data 10 to DVD 60, digital data 10 must go through source code encoder 22, data encryption 32, error correction encoding 42 and modulation 52. Most of the error control encoding uses the Reed-Solomon Product Code (RSPC). Modulation 52 involves performing the Eight-Fourteen Modulation (EMF).
On the other hand, when reading the content stored in the DVD, the content must go through demodulation 54, error correction decoding 44, data decryption 34 and data decoding 24. EFM is used to perform demodulation 54. The error control decoder uses RSPC to decode.
Please refer to FIG. 2(a). FIG. 2(a) illustrates the information field of DVD. DVD information format is made of sectors; each sector is 2064 byte in size. Each information field 70 has 16 sectors, thus as shown in FIG. 2(a), an information field 70 is 172 byte by 192 byte.
Now please look at FIG. 2(b) which illustrates an ECC block. During error correction encoding 42, the outer parity code field 80 of 172 bytes by 16 bytes is added to information field 70. Next, a piece of inner parity code 90 of 10 bytes by 208 bytes is inserted between information field 70 and outer parity code 80. This brings the size of ECC block 100 to 182 bytes by 208 bytes. After EFM modulation, the ECC block can then be recorded to DVD.
Similarly, data read from DVD needs to be demodulated before they could be written into memory in 182 byte by 208 byte chunks and error corrected and decoded.
During error control decoding, the PI in each row is used to detect and correct errors occurred in certain bytes within the same row. For an example, bits B0,172˜B0,181, PI of the row zero of information field 70 is used to correct N bytes of error between B0,0 to B0,171. If greater than N bytes of error occurred, these errors will not be able to be corrected. In this example, when mark erasure is used, 10 bytes of errors can be corrected. When mark erasure is not used, a maximum of 5 bytes can be corrected. The use of PI to perform error correction is known as the PI procedure.
Furthermore, PO could be used to detect and correct certain number bytes of error within the same column. For an example, B192,0˜B207,0 could be used to correct M bytes of error between B0,0 and B191,0. When the number of errors exceeds M between B0,0 and B191,0, they cannot be corrected. In theory, when mark erasure is used, a maximum number of 16 bytes of error could be corrected as oppose to 8 bytes when mark erasure is not used. The procedure of using PO to do correction is known as the PO procedure.
Please now turn to FIG. 3. The illustration depicts an error control decoder device used in prior art DVD devices. The device consists of a data buffer 306 for storing error correction code blocks read from the disk; an error control decoder 310 which further consists an ECC decoder flow controller 312 for controlling the ECC procedure; an ECC engine 314 consisting of a plurality of decoding modules that operate in the manner as a finite state machine in order to decode information with various decoding methods which usually contain at least one PI procedure and at least one PO procedure; an EDC engine 316 for checking errors of target error correction block. The ECC decoder flow controller 312, ECC engine 314 and EDC engine 316 could be implemented with logic circuit or microprocessor microcode. In order to communicate the principal of the present invention, storage medium (such as optical disc, hard disc, and etc.) shown in illustrations and control unit within the storage device are shown as one element called storage medium and control unit 304. The storage medium and control unit 304 exchanges data with host 300 via bus 302.
In prior practice, storage medium and control unit 304 sends not-yet-decoded ECC block to data buffer 306 via bus 302 at the beginning of a decoding session. This block of data sent becomes the “target” ECC block. Next, ECC decoder flow controller 312 initializes and selects either a PI procedure or a PO procedure within the ECC engine 314 and proceeds with decoding. If a PI procedure is selected, EDC engine 316 determines if the block of data passes error correct and terminates the error code control decoder process. Failure in passing the error correct test implies that errors within the target ECC block could not be corrected by the PI procedure. ECC decoder flow controller 312 then check if retry count has met the maximum value; before the retry value reaches the maximum value, ECC decoder flow controller 312 will increment the retry value and proceed with PO procedure.
At the completion of PO procedure, EDC engine 316 performs error detection on the target ECC block. Passing the error detection means data within the target ECC block are correct. This means the target ECC block has had all error corrected and the error code control decoder has completed its task. However if the target ECC block does not pass error detection, it means there are some errors within the block that cannot be corrected with PO procedure. ECC decoder flow controller 312 then check if retry value has met the maximum value; before the retry value reaches the maximum value, ECC decoder flow controller 312 will increment the retry value and proceed with PI procedure. Once the retry value reaches the maximum value, the ECC decoder flow controller 312 will declare an ECC failure since repeating PO and PI procedures were not able to completely correct errors.
Please refer to FIG. 4(a) which depicts the flow of determining failure in prior art. Decoding procedure is initialized before an ECC decoder flow controller 312 can select PI or PO procedure within the error code correction process. As mentioned above, the error code correction process contains at least one PI procedure and at least one PO procedure. Hypothetically, the error detection determines if the ECC block passes error detection procedure 104 after a PI process 102, the information in the block is assumed to be all correct and thus the error correction 114 has been completed and the whole error code control decoding procedure has been completed. Whereas if the ECC block did not pass the error detection test, this implies there are some errors that could not be corrected with PI procedure. Then the retry value is checked (106), if the retry value has not reached the limit, retry value is incremented (107) and PO procedure 108 is carried out.
After PO procedure 108, the error detection coded decoder procedure determines whether the ECC block has passed error detection 110. Passing error detection test 110 means that data in the information sector is correct and has passed error correction 114. Therefore the error detection control decoder procedure could be terminated. On the other hand, if the ECC block did not pass the error detection test, there are some errors the PO procedure could not fix. Then, before the retry value reaches limit (112), retry value is incremented by 1 (113) and PI procedure 102 is carried out. In the case of retry value has reached maximum and the PI and PO procedure did not complete error control decoder procedure, the ECC process has failed (116).
In the previously error control decoding procedures, ECC failure is determined by whether the retry value has reached a certain limit. In some circumstances, for example when (N+1)byte*(M+1) byte of data within the information filed are erroneous, then no matter how many times the device re-attempts to perform error correction, the error control decoding procedure can not be completed. When ECC failure occurs, the target ECC block goes repeating steps 102, 104, 106, 107, 108, 110, 112 and 113 until the retry value reaches limit before reaching ECC failure (116) Thus, a failed error correction could not be identified before the retry value reaches limit. This mechanism could possibly waste system resources by repeating unnecessary PO and PI procedure.
The use of mark erasure provides a better tolerance to errors. Please now turn to FIG. 4(b) which illustrates another known procedure for determining ECC failure. The most significant difference between this drawing and FIG. 4(a) is that the PO and PI procedure in this illustration each have two different approaches. This example has;                1. mark erasure PO procedure 401,        2. mark erasure PI procedure 402,        3. PO procedure without mark erasure 403, and        4. PO procedure PI procedure without mark erasure 404.When a decode failure occurs, the row and column number (YNUM) where failure occurred is noted. When 0<YNUM≦ERA_max (ERA_max is 10 in PI procedure and 16 in PO procedure), another round of mark erasure procedure will be necessary. In this example, when PI procedure 404 results in decode failure, the position is marked and then, (1) mark erasure PO procedure 401 is executed. However, if YNUM is greater than ERA_max (ERA_max in PI procedure is 10 and in PO procedure is 16), another round of decoding procedure without mark erasure should be carried out, which would be (3) PO procedure without mark erasure 403 in the above list.        
When continuous (4) PI procedure without mark erasure 404 and (1) mark erasure PO procedure 401 does not decode all data, the relationship between YNUM and ERA_max are examined again. When 0<YNUM≦ERA_max, (2) mark erasure PI procedure 402 will be performed. On the other hand, if YNUM<ERA_max, then (4) PI procedure without mark erasure 404 would be carried out. Furthermore, if continuous (3)PO procedure without mark erasure 403 and (2) mark erasure PI procedure 402 does not lead to decoding all data, YNUM and ERA_max is compared again to enter into (1) mark erasure PO procedure 401 when 0<YNUM≦ERA_max) or (3) PO procedure without mark erasure 403 if YNUM>ERA_max.
When the ECC block passes error detection after a certain procedure, the data within target ECC block are correct. In other words, the error correction is completed. This means the error control decoding procedure is completed and following procedures are ready to be commenced. Note that this is not illustrated in the drawing. The main disadvantage of the above described flow control is the possibility of missing some opportunities of successfully decoding all data. Please refer to FIG. 5, which is an example of an ECC block with decode failure bytes. Decode failure bytes are marked with “*”. Suppose this ECC block goes through the procedure illustrate by FIG. 4(b), it will, for example, first go through (4) PI procedure without mark erasure 404. When the number of decode failure on a particular row is greater than 5 and smaller than 10, YNUM comes into the picture and helps decide which procedure is to be used next. In this example, YNUM is 8, so 0<YNUM≦ERA_max (ERA_max in PI procedure is 10 and ERA_max in PO is 16) and a round of mark erasure procedure is carried out. In this particular example, decode failure byte after executing PI procedure 404 is marked before ECC block is applied with (1) mark erasure PO procedure 401. Nevertheless, the decode failure row number is very close to the upper limit and there are some data yet to be tested for decode error. The end result is an unsuccessful decoding. This mechanism performs in such a manner that an appropriate PI procedure without mark erasure step 404 will not come into the decoding flow, causing the decoding process to repeat ineffectively. The purpose of the present invention improves on the above mention flaws of prior art.